7.7 Enterprise-grade 6x fast read and 5x highly reliable SSD with TLC NAND-flash memory for big-data storage

Author

Tokutomi, Tsukasa ; Doi, Masafumi ; Hachiya, Shogo ; Kobayashi, Atsuro ; Tanakamaru, Shuhei ; Takeuchi, Ken

Author_Institution

Chuo Univ., Tokyo, Japan

fYear

2015

fDate

22-26 Feb. 2015

Firstpage

1

Lastpage

3

Abstract

An enterprise-grade SSD with TLC (3b/cell) NAND Flash is presented with three techniques that achieve high speed and high reliability. Quick low-density parity-check (LDPC) reduces the read latency of 1Xnm TLC NAND Flash SSD by 83%. Dynamic V_TH optimization and auto data recovery reduce the NAND Flash bit-error rate (BER) by 80% and 18%, respectively. These techniques can be implemented in the SSD controller without circuit overhead. No modification is required to the TLC NAND flash.

Keywords

Big Data; dynamic programming; error statistics; flash memories; BER; Big-Data storage; LDPC; NAND flash bit-error rate reduction; TLC NAND flash SSD controller; TLC NAND-flash memory; autodata recovery; circuit overhead; dynamic V_TH optimization; enterprise-grade SSD; low-density parity-check; read latency reduction; Bit error rate; Error correction codes; Flash memories; Optimization; Parity check codes; Reliability; Sensors;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid- State Circuits Conference - (ISSCC), 2015 IEEE International

Conference_Location

San Francisco, CA

Print_ISBN

978-1-4799-6223-5

Type

conf

DOI

10.1109/ISSCC.2015.7062965

Filename

7062965