A system for electromigration analysis in VLSI metal patterns

Author

Hajj, I.N. ; Rao, V.B. ; Iimura, R. ; Cha, H. ; Burch, R.

Author_Institution

Illinois Univ., Urbana, IL, USA

fYear

1991

fDate

12-15 May 1991

Abstract

The authors describe a CAD (computer-aided design) system for reliability analysis of VLSI CMOS circuits, with emphasis on electromigration estimation in power and ground metal lines. The system consists of three main components: extraction of circuit netlist and parameters and RC line models from layout; calculation of expected or average current waveforms drawn by the circuit at the contacts of the buses; and computation of average current densities in sections of the power and ground buses for electromigration estimation. The system tools have been integrated around the Berkeley OCT/VEM design framework system

Keywords

CMOS integrated circuits; VLSI; circuit CAD; circuit reliability; electromigration; electronic engineering computing; metallisation; Berkeley OCT/VEM design framework; CAD; CMOS circuits; RC line models; VLSI metal patterns; computer-aided design; current densities; current waveforms; electromigration analysis; ground metal lines; netlist extraction; parameter extraction; power metal lines; reliability analysis; Circuit synthesis; Current density; Data mining; Design automation; Electromigration; Integrated circuit interconnections; Integrated circuit reliability; Pattern analysis; Power system reliability; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0015-7

Type

conf

DOI

10.1109/CICC.1991.164005

Filename

164005