Pre-Route Interconnect Capacitance and Power Estimation in FPGAs

The increase in functional complexity and performance requirements of reconfigurable fabrics has necessitated the early estimation of power distribution to explore power aware architectures and design techniques. In this work, we make several contributions to interconnect power estimation in FPGAs. First we present a probabilistic methodology that uses demand, a parameter reflecting the probable usage of a routing resource, to estimate interconnect capacitance and dynamic power dissipation. We then extend this model to estimate static power distribution of interconnect resources. Finally, the framework of our model also allows us to estimate spatial power distribution. Our results indicate accurate predictions with average errors of 7, 11 and 7 percent for capacitance, dynamic and static power respectively.