DocumentCode
2062254
Title
Exploiting Hardware and Software Low power Techniques for Energy Efficient Co-Scheduling in Dynamically Reconfigurable Systems
Author
Hsiung, Pao-Ann ; Liu, Chih-Wen
Author_Institution
Nat. Chung Cheng Univ., Chiayi
fYear
2007
fDate
27-29 Aug. 2007
Firstpage
165
Lastpage
170
Abstract
Currently, the hardware and the software tasks in reconfigurable systems are either scheduled separately at run time or co-scheduled statically, which results in high power consumption and low performance. This work proposes runtime co-scheduling of hardware and software tasks by using the slack time, which is introduced due to reusing hardware task configurations, for dynamically scaling the processor voltage such that preceding software tasks consume lesser power. At the same time, the reuse of hardware task configurations also result in lower power consumption and higher performance due to fewer number of reconfigurations. The combined effects of hardware configuration reuse and software dynamic voltage scaling result in schedules with a lower power consumption and higher performance than that obtained through individual techniques applied to hardware and software separately. The proposed method was implemented in the SystemC-based Perfecto simulation environment for dynamically reconfigurable hardware software systems and TGFF was used for generating random task sets as input for Perfecto. We performed extensive experiments whose results show that irrespective of different slack ratios or hardware partitions, the schedules generated by our proposed method are more energy efficient than methods that either do not apply any runtime techniques or only apply hardware configuration prefetch and reuse.
Keywords
digital simulation; hardware description languages; power aware computing; reconfigurable architectures; SystemC-based Perfecto simulation; reconfigurable hardware software system; reconfigurable system; runtime co-scheduling; software dynamic voltage scaling; Dynamic scheduling; Dynamic voltage scaling; Energy consumption; Energy efficiency; Hardware; Prefetching; Processor scheduling; Runtime; Software performance; Software systems;
fLanguage
English
Publisher
ieee
Conference_Titel
Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on
Conference_Location
Amsterdam
Print_ISBN
978-1-4244-1060-6
Electronic_ISBN
978-1-4244-1060-6
Type
conf
DOI
10.1109/FPL.2007.4380642
Filename
4380642
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