High fault coverage of in-circuit IC pin faults with a vectorless test technique using parasitic transistors

A vectorless test technique has been developed that uses a simple transistor test to detect and isolate I/O related faults on all types of ICs, from simple devices to complex ASICs, that has the advantage of providing high fault coverage without using function test as a back-up. The parasitic transistor test (PTT) technique makes use of the inherent bipolar transistor effect that exists between X/O pins on all types of monolithic ICs. Tests are performed without applying power to the board and without the need to backdrive ICs, as is normally required for in-circuit functional test techniques. Programming effort is minimal, since it is not necessary to model the ICs or know their functionality. To test an IC, a simple three pin transistor test is performed and then repeated around the device until all pins on the device have been used in at least one three-pin test. By properly biasing the pins used in each test, an active transistor current can be generated and measured to determine the integrity of the connection of those three pins