Abstract :
Designers of FPGA-based systems are increasingly including soft processors-processors implemented in programmable logic-in their designs. Any combination of area, clock frequency, performance, and power may be of importance in the choice of a soft processor design to use, motivating area efficiency as the best metric with which to compare potential designs. In this paper we demonstrate that 3, 5, and 7-stage pipelined multithreaded soft processors are 33%, 77%, and 106% more area efficient than their single-threaded counterparts, the result of careful tuning of the architecture, ISA, and number of threads.
Keywords :
field programmable gate arrays; logic design; multi-threading; pipeline processing; FPGA-based system; field programmable gate array; multithreading; pipelined soft processor; programmable logic; Clocks; Field programmable gate arrays; Frequency; Instruction sets; Logic; Multithreading; Pipelines; Process design; System-on-a-chip; Yarn;
