Title :
RIDDLE: a foundation for test generation on a high level design description
Author :
Silberman, G.M. ; Spillinger, I.
Author_Institution :
Technion, Israel Inst. of Technol., Haifa, Israel
Abstract :
A formal approach is presented to the analysis of a VLSI design described at the high level, which produces information conducive to the acceleration of test-generation algorithms. This analysis yields information which can be used to reduce the amount of effort expended during backtracking, by guiding this process towards decisions (assignments) less likely to cause conflicts and minimizing the amount of work between backtracks. RIDDLE, an algorithm that performs this analysis in time that is linear in the number of signals, is introduced. Experimental results for the special case of combinatorial gate-level designs are also given.<>
Keywords :
VLSI; combinatorial circuits; integrated logic circuits; logic testing; RIDDLE; VLSI; combinatorial gate-level designs; test generation; Algorithm design and analysis; Circuit testing; Complexity theory; Computer science; Information analysis; Life estimation; Performance analysis; Signal analysis; Test pattern generators; Very large scale integration;
Conference_Titel :
Fault-Tolerant Computing, 1988. FTCS-18, Digest of Papers., Eighteenth International Symposium on
Conference_Location :
Tokyo, Japan
Print_ISBN :
0-8186-0867-6
DOI :
10.1109/FTCS.1988.5300
