Title :
Design of an eFuse OTP memory of 8 bits based on a 0.35µm BCD process
Author :
Park, Young-Bae ; Choi, In-Hwa ; Lee, Dong-Hoon ; Jin, Liyan ; Jang, Ji-Hye ; Ha, Pan-Bong ; Kim, Young-Hee
Author_Institution :
Dept. of Electron. Eng., Changwon Nat. Univ., Changwon, South Korea
Abstract :
In this paper, we design an 8-bit eFuse OTP (one-time programmable) memory based on a BCD process using differential paired eFuse cells which can sense BL data without a reference voltage and also have smaller sensing resistances of programmed eFuse links. Also, we implement a sensing margin test circuit with variable pull-up loads in consideration of variations of the programmed eFuse resistances. The layout size of the designed 8-bit eFuse OTP memory IP is 142μm × 380.725μm.
Keywords :
circuit testing; random-access storage; BCD process; differential paired eFuse cells; eFuse OTP memory; one-time programmable memory; size 0.35 mum; IP networks; Layout; MOSFETs; Programming; Resistance; Sensors;
Conference_Titel :
Mobile IT Convergence (ICMIC), 2011 International Conference on
Conference_Location :
Gyeongsangbuk-do
Print_ISBN :
978-1-4577-1128-2
Electronic_ISBN :
978-89-88678-61-9
