DocumentCode
2063150
Title
Parallel Viterbi decoding by breaking the compare-select feedback bottleneck
Author
Fettweis, Gerhard ; Meyr, Heinrich
Author_Institution
Aachen Univ. of Technol., West Germany
fYear
1988
fDate
12-15 Jun 1988
Firstpage
719
Abstract
A solution is presented for implementing the add-compare-select (ACS) unit of a Viterbi decoder by parallel hardware for high data rates. For a fixed processing speed of the given hardware it allows a linear increase in throughput rate by a linear increase in hardware complexity. Thus arbitrary throughput rates can be achieved by linearly adding more parallel hardware elements. A systolic-array implementation of this parallel ACS unit of a Viterbi decoder is presented
Keywords
decoding; Viterbi decoder; add-compare-select; compare-select feedback bottleneck; high data rates; parallel Viterbi decoding; parallel hardware; systolic-array implementation; throughput; Convolutional codes; Decoding; Feedback loop; Hardware; Markov processes; Pipeline processing; Probability; Systolic arrays; Throughput; Viterbi algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications, 1988. ICC '88. Digital Technology - Spanning the Universe. Conference Record., IEEE International Conference on
Conference_Location
Philadelphia, PA
Type
conf
DOI
10.1109/ICC.1988.13656
Filename
13656
Link To Document