Title :
Hardware architecture for real-time HD(1920×1080@60fps) H.264/AVC intra prediction
Author :
Park, Seung Ho ; Lee, Jae Hun
Author_Institution :
Digital Media R&D Center, Samsung Electron. Co., Ltd., Seoul
Abstract :
In this paper, we propose a hardware architecture for a real time H.264/AVC intra predictor generator that can support 1920times1080@60fps. The proposed hardware architecture can generate 16 intra predictors for all 4 times 4 and 16 times 16 intra prediction modes in one clock, in comparison, previous implementations could only generate 4 predictors.
Keywords :
code standards; high definition video; video coding; H.264-AVC intra predictor generator; hardware architecture; high definition video; real-time HD advanced video coding; Automatic voltage control; Clocks; Hardware; ISO standards; MPEG 4 Standard; Research and development; Standards development; Very large scale integration; Video coding; H.264/AVC; VLSI design; intra prediction;
Conference_Titel :
Consumer Electronics, 2008. ISCE 2008. IEEE International Symposium on
Conference_Location :
Vilamoura
Print_ISBN :
978-1-4244-2422-1
Electronic_ISBN :
978-1-4244-2422-1
DOI :
10.1109/ISCE.2008.4559505
