Design of LDPC graphs for hardware implementation

A methodology for generating bipartite graphs for LDPC codes which both exhibit good performance under message passing decoding and are amenable to direct hardware implementation is described. To this end, we define a novel quantitative measure of the "loopiness" of a graph, as well as a quantitative measure of the cost of direct hardware implementation, and use the well-known simulated annealing algorithm to simultaneously minimize both quantities. Finally, we simulate the decoding of several rather short codes to show that the performance is indeed predicted by our loopiness measure.