Title :
Design and performance analysis of shift register-based ATM switch
Author :
Elguibaly, Fayez ; Agarval, S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada
Abstract :
We present a modified design of the shift register-based ATM switch introduced by El-Guibaly, Sabaa and Shpak (see IEEE ETACOM ´96, p.24-7, 1996). The switch design has been modified to perform connection admission control (signalling) and management (OAM) functions. This switch overcomes the HOL and low throughput problems and supports QOS and multicasting functions. The internal details of each module of the switch architecture are presented. Also, a performance analysis of the switch is done to find the cell loss probability and throughput
Keywords :
asynchronous transfer mode; buffer storage; electronic switching systems; probability; shift registers; telecommunication congestion control; telecommunication network management; telecommunication services; telecommunication signalling; OAM; QOS; cell loss probability; connection admission control; management; multicasting functions; performance analysis; shift register based ATM switch; signalling; switch architecture; switch design; throughput; Admission control; Asynchronous transfer mode; Buffer storage; Performance analysis; Queueing analysis; Shift registers; Signal design; Smoothing methods; Switches; Throughput;
Conference_Titel :
Communications, Computers and Signal Processing, 1997. 10 Years PACRIM 1987-1997 - Networking the Pacific Rim. 1997 IEEE Pacific Rim Conference on
Conference_Location :
Victoria, BC
Print_ISBN :
0-7803-3905-3
DOI :
10.1109/PACRIM.1997.619905
