Multi-width fixed-point coding based on reprogrammable hardware implementation of a multi-layer perceptron neural network for alertness classification

This paper presents an optimizing methodology for implementing a multi-layer perceptron (MLP) neural network in a Field Programmable Gate Array (FPGA) device. In order to obtain an efficient implementation, a compromise of time and area is needed. Starting from simulation in the learning phase with fixed point operators, we have developed a methodology which allows the automatic generation of a VHDL code within a multi-width encoding of an MLP. The proposed methodology should determine the optimal encoding of various blocks of our Artificial Neural Networks (ANN) to optimize accuracy and minimize the application area. In addition, real-time constraints should be respected to ensure a reliable classification of vigilance states in humans from electroencephalographic signals (EEG). To validate our approach, the optimized MLP implementation has been tried on Virtex devices.