Low power instruction cache design based on branch execution tracks

Power consumption is a major consideration in embedded microprocessor design. This paper presents a low power design approach of instruction cache based on branch execution tracks. The approach utilizes the recorded branch execution tracks to determine whether or not the referenced instructions reside in the instruction cache, and attempts to eliminate the unnecessary tag checks at runtime. Moreover, a novel method for maintaining the branch execution tracks effectively at cache size level is proposed. Experimental results of SuperV DSP show that this approach could reduce 96.64% of tag checks and save 19.71% of instruction cache power consumption, with only 2.16% of area increasing and no performance degradation.