• DocumentCode
    2063519
  • Title

    H. 264 Decoder at HD Resolution on a Coarse Grain Dynamically Reconfigurable Architecture

  • Author

    Ganesan, Angamuthu ; Singh, Sundeep ; May, Frank ; Becker, Jürgen

  • Author_Institution
    PACT XPP Technol. AG, Munich
  • fYear
    2007
  • fDate
    27-29 Aug. 2007
  • Firstpage
    467
  • Lastpage
    471
  • Abstract
    The extreme processing platform (XPP) is a new runtime-reconfigurable data processing architecture. It is based on a scalable array of coarse grained computing elements and a packet oriented communication network. The strength of XPP originates from the combination of array processing with unique, powerful runtime-reconfiguration mechanisms. Parts of the array can be configured rapidly in parallel while neighboring computing elements are processing data. Reconfiguration is triggered by internal event signals, or by a function processing array element (FNC-PAE). The XPP-III architecture is designed to support pipelining and parallelism: instruction-level, dataflow and task-level parallelism. The control flow is handled by multiple VLIW like processors which are closely coupled to the reconfigurable array. Therefore this technology is very well suited for multimedia, telecommunications, graphics and similar stream-based applications with data and control flow. This paper presents the performance of H.264/AVC decoder on XPP-III. The simulation results are very encouraging and allow up to HD (1920x1080@24fps) decoding on the XPP-III architecture.
  • Keywords
    decoding; instruction sets; reconfigurable architectures; video codecs; video coding; H.264 decoder; XPP-III architecture; coarse grained computing element; extreme processing platform; function processing array element; instruction-level parallelism; internal event signals; multiple VLIW; packet oriented communication network; runtime-reconfigurable data processing architecture; task-level parallelism; video codecs; Communication networks; Computer architecture; Computer networks; Data processing; Decoding; High definition video; Parallel processing; Reconfigurable architectures; Streaming media; Telecommunication control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on
  • Conference_Location
    Amsterdam
  • Print_ISBN
    978-1-4244-1060-6
  • Electronic_ISBN
    978-1-4244-1060-6
  • Type

    conf

  • DOI
    10.1109/FPL.2007.4380691
  • Filename
    4380691