DocumentCode :
2063578
Title :
Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors
Author :
Matsuno, Shogo ; Tawada, Masashi ; Yanagisawa, M. ; Kimura, Shunji ; Togawa, N. ; Sugibayashi, Tadahiko
Author_Institution :
Waseda Univ., Tokyo, Japan
fYear :
2013
fDate :
28-31 Oct. 2013
Firstpage :
1
Lastpage :
4
Abstract :
As leakage power of traditional SRAM becomes larger, a ratio of static energy in total energy of memory architecture becomes also larger. Non-volatile memory (NVM) has many advantages over SRAM, such as high density, low leakage power, and non-volatility, but consumes too much write energy. In this paper, we evaluate energy consumption of two-level cache using NVM in part on mobile processors and confirm that it effectively reduces energy consumption.
Keywords :
SRAM chips; cache storage; NVM; energy consumption evaluation; energy evaluation; leakage power; memory architecture; mobile processors; nonvolatile memory; static energy ratio; traditional SRAM; two-level cache; two-level on-chip cache; write energy; Computational modeling; Computer architecture; Energy consumption; Mobile communication; Nonvolatile memory; Program processors; Random access memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC (ASICON), 2013 IEEE 10th International Conference on
Conference_Location :
Shenzhen
ISSN :
2162-7541
Print_ISBN :
978-1-4673-6415-7
Type :
conf
DOI :
10.1109/ASICON.2013.6811826
Filename :
6811826
Link To Document :
بازگشت