Leakage current minimization in dynamic circuits using sleep switch

A new circuit technique is proposed in this literature to simultaneously reduce subthreshold leakage as well as gate-oxide leakage in ultra-deep submicron technology, as gate leakage is dominant for ultra thin gate insulating layer (i.e. t_ox >; 20Å̊). Here we are using the dual threshold voltage technique to reduce the leakage current as well as propagation delay and sleep switches to further reduce leakage current. We observed the further leakage current reduction of about 11.21% by using proposed DTPMOS sleep switch, and by using proposed stacked PMOS sleep switch is about 37.63%. Whereas, further reduction in propagation delay by using DTPMOS sleep is about 16.87% and by using stacked PMOS is about 14.97%. We have also seen that the discharging of dynamic node is more for DTMOS configuration, which is advantageous in term of reduction in leakage current when we will use multistage cascaded configuration.