14.4 A 5GHz −95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS

Since the advent of digital PLLs (DPLLs), various techniques have been proposed for a low-power, low-noise fractional-N frequency synthesizer. Among the various innovations, a reference-multiplied architecture offers distinct advantages compared to conventional DPLLs [1]. First, low quantization noise (q-noise) can be achieved without complex q-noise cancellation schemes, since the delta-sigma modulator (DSM) has a high oversampling ratio and its q-noise is pushed to higher frequencies. Second, noise requirements of PLL building blocks become less stringent as the division value is reduced. For a digital PLL using a Nyquist-rate time-to-digital converter (TDC), if the reference is multiplied by N the time resolution of the TDC can be reduced by √N for the same noise level. Unfortunately, one drawback of the reference-multiplied PLL is the increase in power and complexity due to the reference-multiplying circuit. In this paper, we propose a reference-multiplied digital fractional-N PLL that has negligible overhead in the reference-multiplying circuit. To save power, a frequency-multiplied TDC (FMTDC) consisting of an open-loop multiplying DLL (MDLL) and a Vernier delay-line (VDL) TDC is proposed, which share their delay lines. High spurious tone coming from the open-loop MDLL is canceled by an adaptive filter located between TDC and loop filter.