14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S

All-digital phase-locked loops (ADPLLs) offer faster locking time, easier portability and better performance in advanced semiconductor processes as compared to analog PLLs. Advanced FinFET devices exhibit better g_m and I_ON than planar devices [1], but they are offered only in a limited number of device sizes, thus precluding their use in traditional analog design styles. In an ADPLL, the transistors are used as switches with little regard to their linear analog properties. Hence, ADPLL performance should improve with the adoption of FinFET devices. Inverter delay in a 16nm FinFET process is less than half of that in a 28nm planar process, improving in-band phase noise (PN) by around 6dB [2]. Ring-type digitally controlled oscillators (DCOs) provide wide frequency tuning range (FTR), but poor PN performance degrades the ADPLL figure of merit (FoM) [3]. Achieving an FoM better than -225dB using a ring DCO is a challenge. In this work, we presenta 0.25-to-4GHz, 1.22ps integrated jitter and -228.6dB FoM fractional-N ADPLL with spread-spectrum clocking (SSC) capability in 16nm FinFET CMOS.