Design of FPGA based digital controller for 2nd and higher order systems

Author

Adhikary, Avishek ; Khanra, Munmun ; Biswas, Karabi

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Technol. (IIT) Kharagpur, Kharagpur, India

fYear

2012

fDate

16-18 March 2012

Firstpage

1

Lastpage

5

Abstract

This paper describes a new method for designing digital controller and their FPGA based realization schemes. The design method is based on time domain response to meet three different time domain specifications settling time, peak overshoot/rise time and closed loop gain ensuring minimal ITAE. This design method follows Graham Lathrop optimal polynomials (GL Polynomials) with an introduction of Left Hand Side zero (LHS Zero). The same design method to be applicable for any system from 2nd to 6th order. Simulation results of tests for robustness and specifications change also featured in this paper.

Keywords

digital control; field programmable gate arrays; polynomials; FPGA based digital controller; FPGA based realization scheme; Graham Lathrop optimal polynomials; closed loop gain; higher order system; left hand side zero; peak overshoot/rise time; time domain response; time domain specification settling time; Algorithm design and analysis; Control systems; Delay; Design methodology; Field programmable gate arrays; Frequency response; Transfer functions; 2nd to 6th order systems; Digital controller; FPGA based realization; GL Polynomials; LHS zero; Minimal ITAE; Robust Controller; Time response specifications;

fLanguage

English

Publisher

ieee

Conference_Titel

Engineering and Systems (SCES), 2012 Students Conference on

Conference_Location

Allahabad, Uttar Pradesh

Print_ISBN

978-1-4673-0456-6

Type

conf

DOI

10.1109/SCES.2012.6199059

Filename

6199059