14.6 An all-digital power-delivery monitor for analysis of a 28nm dual-core ARM Cortex-A57 cluster

The current trend for System-on-Chip (SoC) compute subsystems is to improve energy efficiency, while operating at a similar power budget as previous generations. Reduced supply voltages and increased transistor density affords SoCs composed of multiple clusters of CPUs and additional specialized compute engines. However, this comes at the cost of both increasing current, and increasing current density, to the extent that these systems are ultimately constrained by power delivery. Pathological AC supply noise conditions may arise due to sporadic combinations of system and micro-architectural events, and these effectively limit the energy efficiency of the system, as sufficient voltage margin must be deployed to guarantee these conditions do not result in system failure.