• DocumentCode
    2063905
  • Title

    Test considerations for BiCMOS logic families

  • Author

    Roy, Kaushik ; Levitt, Marc E. ; Abraham, Jacob A.

  • Author_Institution
    Texas Instrum., Dallas, TX, USA
  • fYear
    1991
  • fDate
    12-15 May 1991
  • Abstract
    The testability of various BiCMOS logic families is examined. For each design style the adequacy of stuck-at and quiescent current testing is explored. It is shown that while stuck-at and Iddq testing can cover many faults there are still a large number of faults that are not detectable. Using the results presented the various logic families can be ranked by testability when being evaluated for an application
  • Keywords
    BIMOS integrated circuits; application specific integrated circuits; integrated circuit testing; logic testing; BiCMOS; delay faults; logic families; quiescent current testing; stuck-at faults; stuck-at testing; test considerations; testability; Application specific integrated circuits; BiCMOS integrated circuits; CMOS technology; Circuit faults; Circuit testing; Delay; Fault detection; Inverters; Logic testing; MOS devices;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
  • Conference_Location
    San Diego, CA
  • Print_ISBN
    0-7803-0015-7
  • Type

    conf

  • DOI
    10.1109/CICC.1991.164011
  • Filename
    164011
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2063905