A High Speed License Plate Recognition System on an FPGA

Author

Kanamori, Takamasa ; Amano, Hideharu ; Arai, Masatoshi ; Ajioka, Yoshiaki

Author_Institution

Keio Univ. Yokohama, Yokohama

fYear

2007

fDate

27-29 Aug. 2007

Firstpage

554

Lastpage

557

Abstract

A high speed FPGA off-loading engine for detecting the license plate itself in order to avoid the traffic accident is proposed. A complicated algorithm is written in Handel-C, and parallel processing is explicitly utilized in every level of implementation; an input image is segmented into 16 areas, and each area is processed in parallel by a multiple calculation unit executing pipeline processing and a distributed memory module. A prototype circuit implemented on a general purpose FPGA board achieved 4.16 times performance as software execution on a Pentium-Ill desktop PC. The highest performance in literature; 100 frames per second; can be achieved.

Keywords

distributed memory systems; field programmable gate arrays; image recognition; image segmentation; parallel processing; FPGA; Handel-C; Pentium-desktop Ill PC; distributed memory module; high speed license plate recognition system; multiple calculation unit; parallel processing; pipeline processing; traffic accident; Circuits; Engines; Field programmable gate arrays; Image segmentation; Licenses; Parallel processing; Pipeline processing; Road accidents; Software performance; Software prototyping;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on

Conference_Location

Amsterdam

Print_ISBN

978-1-4244-1060-6

Electronic_ISBN

978-1-4244-1060-6

Type

conf

DOI

10.1109/FPL.2007.4380715

Filename

4380715