A High Speed License Plate Recognition System on an FPGA

A high speed FPGA off-loading engine for detecting the license plate itself in order to avoid the traffic accident is proposed. A complicated algorithm is written in Handel-C, and parallel processing is explicitly utilized in every level of implementation; an input image is segmented into 16 areas, and each area is processed in parallel by a multiple calculation unit executing pipeline processing and a distributed memory module. A prototype circuit implemented on a general purpose FPGA board achieved 4.16 times performance as software execution on a Pentium-Ill desktop PC. The highest performance in literature; 100 frames per second; can be achieved.