Title :
Implementation of a 2-D 8Ã\x978 IDCT on the Reconfigurable Montium Core
Author :
Smit, L.T. ; Rauwerda, G.K. ; Molclerink, A. ; Wolkotte, P.T. ; Smit, G.J.M.
Author_Institution :
Recore Syst., Enschede
Abstract :
This paper describes the mapping of a two-dimensional inverse discrete cosine transform (2-D IDCT) onto a word-level reconfigurable Montiumreg processor. This shows that the IDCT is mapped onto the Montium tile processor (TP) with reasonable effort and presents performance numbers in terms of energy consumption, speed and silicon costs. The Montium results are compared with the IDCT implementation on three other architectures: TI DSP, ASIC and ARM.
Keywords :
digital signal processing chips; discrete cosine transforms; reconfigurable architectures; ARM; ASIC; Montium tile processor; reconfigurable Montium core; two-dimensional inverse discrete cosine transform; word-level reconfigurable Montium processor; CMOS technology; Computer architecture; Costs; Decoding; Digital signal processing; Discrete cosine transforms; Energy consumption; Signal processing algorithms; Silicon; Tiles;
Conference_Titel :
Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on
Conference_Location :
Amsterdam
Print_ISBN :
978-1-4244-1060-6
Electronic_ISBN :
978-1-4244-1060-6
DOI :
10.1109/FPL.2007.4380717
