Title :
Timing driven routing and resistivity minimization
Author_Institution :
Cadence Design Syst. Inc., Santa Clara, CA, USA
Abstract :
Two resistivity minimization routines that can be used for performance optimization during the routing stage are presented. The first optimizer, the topological resistivity minimizer (TRM), is lowcost and rearranges wires to minimize the length of high-resistivity wires (usually poly). The second one, the constrained resistivity minimizer (CRM), fixes the topology and uses layer assignment techniques to reduce the poly length. Since extra contacts are generally inserted, this optimizer can be expensive. Assuming that 10% of the nets are critical in a 2-1/2 layer design, the total poly length of these nets can be reduced by 4.9 times while increasing the routing area by only 1%
Keywords :
VLSI; circuit layout CAD; network topology; wiring; constrained resistivity minimizer; high-resistivity wires; layer assignment techniques; performance optimization; poly length; resistivity minimization routines; routing area; routing stage; topological resistivity minimizer; Conductivity; Constraint optimization; Cost function; Delay; Design optimization; Modems; Routing; Timing; Transmission line measurements; Wires;
Conference_Titel :
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0015-7
DOI :
10.1109/CICC.1991.164012