DocumentCode :
2064294
Title :
A novel phase detection system for linear all-digital phase locked loop
Author :
Das, Abhishek ; Dash, Suraj ; Babu, B. Chitti ; Sahoo, Ajit Kumar
Author_Institution :
Dept. of Electron. & Commun. Eng., Nat. Inst. of Technol., Rourkela, India
fYear :
2012
fDate :
16-18 March 2012
Firstpage :
1
Lastpage :
6
Abstract :
In this paper, a novel fast phase detection system for all-digital phase locked loop (ADPLL) is presented. The phase detection system is realized by generating an analytic signal using a compact implementation of Hilbert transform and then simply computing the instantaneous phase. 16-bit CORDIC algorithm is employed in order to obtain the phase information of the signal. All the components used in this phase detection system are realized as digital discrete time components. This design does not involve any class of multipliers thus reducing the complexity of the design. The phase detection system although providing a definite advantage over conventional analog phase detectors, the Hilbert filter implemented in this paper has been designed using a method based on complex, multiplier less sampling filters. A comparison has been drawn between the continuous PLL model´s phase detection system and the proposed method for effectiveness of the study. The studied system is modeled and tested in the MATLAB/Simulink environment.
Keywords :
Hilbert transforms; digital arithmetic; digital phase locked loops; filtering theory; multiplying circuits; phase detectors; signal sampling; CORDIC algorithm; Hilbert filter; Hilbert transform; MATLAB-Simulink environment; analog phase detector; analytic signal generation; complex multiplier less sampling filter; digital discrete time component; fast phase detection system; linear all-digital phase locked loop; signal phase information; word length 16 bit; Band pass filters; Filtering algorithms; Finite impulse response filter; IIR filters; Information filters; Phase detection; Phase locked loops; CORDIC algorithm; Hilbert Transform; Phase detector; Phase locked loop; Signal processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Engineering and Systems (SCES), 2012 Students Conference on
Conference_Location :
Allahabad, Uttar Pradesh
Print_ISBN :
978-1-4673-0456-6
Type :
conf
DOI :
10.1109/SCES.2012.6199080
Filename :
6199080
Link To Document :
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