Hardware/Software Process Migration and RTL Simulation

This paper describes an execution cache that uses process migration between hardware and software contexts by way of run-time reconfiguration (RTR) of Field Programmable Gate Arrays (FPGAs). The feasibility of such a system is demonstrated using existing FPGAs by accelerating a cycle-based simulation of a Register Transfer Level (RTL) design description. Through the use of a common instruction set, each simulation process may be run in a software Virtual Machine (VM) or in a hardware Real Machine (RM). The implementation provides data for an empirical model used to examine the behavior of unimplemented parts of the system.