17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access

Author

Fredeman, Gregory ; Plass, Donald ; Mathews, Abraham ; Reyer, Kenneth ; Knips, Thomas ; Miller, Thomas ; Gerhard, Elizabeth ; Kannambadi, Dinesh ; Paone, Chris ; Dongho Lee ; Rainey, Daniel ; Sperling, Michael ; Whalen, Michael ; Burns, Steven

Author_Institution

IBM, Poughkeepsie, NY, USA

fYear

2015

fDate

22-26 Feb. 2015

Firstpage

1

Lastpage

3

Abstract

IBM introduced trench capacitor eDRAM into its high performance microprocessors beginning with 45nm and Power 7 [1] to provide a higher density cache without chip crossings. Whereas the 45 and 32nm designs employ a micro sense amplifier [2] and three-level bitline hierarchy, the design implemented for 22nm utilizes a higher gain sense amplifier and two-level bitline architecture that together provide significant reductions in area, latency, and power. This 22nm design style has been migrated into a 14nm FinFET [3] learning vehicle, complete with an ABIST engine, wordline charge pumps (VPP and VWL), and padcage interface circuitry.

Keywords

DRAM chips; MOSFET; charge pump circuits; embedded systems; ABIST engine; FinFET learning vehicle; IBM; VPP; VWL; area reduction; density cache; design style; embedded DRAM macro; high performance microprocessors; latency reduction; microsense amplifier; padcage interface circuitry; power reduction; size 14 nm; size 22 nm; size 32 nm; size 45 nm; three-level bitline hierarchy; time 1 ns; trench capacitor eDRAM; two-level bitline architecture; wordline charge pumps; Capacitors; Charge pumps; Clocks; Computer architecture; FinFETs; Logic gates; Microprocessors;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid- State Circuits Conference - (ISSCC), 2015 IEEE International

Conference_Location

San Francisco, CA

Print_ISBN

978-1-4799-6223-5

Type

conf

DOI

10.1109/ISSCC.2015.7063053

Filename

7063053