Author_Institution :
Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
Abstract :
This paper describes a random access memory (RAM, sometimes also called an array) test scheme that has the following attributes: it can be used in both built-in mode and off chip/module mode; it can be used to test and diagnose naked arrays; fault diagnosis is simple and is “free” for some faults during test; it is never subject to aliasing; depending upon the test length, it can detect many kinds of failures; like stuck-cells, decoder faults, shorts, pattern-sensitive, etc; if used as built-in feature, it does not slow down the normal operation of the array; it does not require storage of correct responses; a single response bit always indicates whether a fault has been detected; the storage requirement for the implementation of the test scheme is zero; if used as a built-in feature, the hardware overhead is very low
Keywords :
built-in self test; design for testability; fault diagnosis; integrated circuit testing; integrated memory circuits; logic testing; random-access storage; RAM BIST; aliasing; built-in feature; couple cell faults; decoder faults; fault diagnosis; hardware overhead; naked arrays; off chip/module mode; pattern-sensitive faults; response bit; shorts; stuck-cells; testable structure; Built-in self-test; Circuit testing; Costs; Failure analysis; Fault detection; Fault diagnosis; Jacobian matrices; Lakes; Random access memory; Read-write memory;
Conference_Titel :
Instrumentation and Measurement Technology Conference, 2000. IMTC 2000. Proceedings of the 17th IEEE
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-5890-2
DOI :
10.1109/IMTC.2000.846854
