Title :
A 20 Gb/s Limiting Amplifier in 65nm CMOS technology
Author :
Rui He ; Jianfei Xu ; Na Yan ; Min Hao
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Abstract :
This paper presents a 20Gb/s Limiting Amplifier (LA) with the active interleaving feedback technique both to broaden the bandwidth and achieve flatness response. The LA includes an input match and DC offset cancellation (DCOC), a four-stage 3rd order amplifier core and an output buffer for test. Simulated in the 65nm CMOS technology, the LA exhibits a voltage gain of 38.5dB, a 3-dB bandwidth of 18GHz and an integrated input noise of 0.56mV with the area of only 0.45 × 0.25 mm2. The chip excluding buffer is supplied by 1.2V VDD and consumes DC power of 61mW.
Keywords :
CMOS analogue integrated circuits; MMIC amplifiers; circuit feedback; field effect MMIC; microwave limiters; CMOS technology; DC offset cancellation; DCOC; LA; active interleaving feedback technique; bit rate 20 Gbit/s; four-stage 3rd order amplifier; frequency 18 GHz; gain 38.5 dB; limiting amplifier; output buffer; power 61 mW; size 65 nm; voltage 0.56 mV; voltage 1.2 V; Bandwidth; CMOS integrated circuits; CMOS technology; Gain; Limiting; Noise; Resistors;
Conference_Titel :
ASIC (ASICON), 2013 IEEE 10th International Conference on
Conference_Location :
Shenzhen
Print_ISBN :
978-1-4673-6415-7
DOI :
10.1109/ASICON.2013.6811865
