18.6 A 0.5nJ/pixel 4K H.265/HEVC codec LSI for multi-format smartphone applications

Author

Chi-Cheng Ju ; Tsu-Ming Liu ; Kun-Bin Lee ; Yung-Chang Chang ; Han-Liang Chou ; Chin-Ming Wang ; Tung-Hsing Wu ; Hue-Min Lin ; Yi-Hsin Huang ; Chia-Yun Cheng ; Ting-An Lin ; Chun-Chia Chen ; Yu-Kun Lin ; Min-Hao Chiu ; Wei-Cing Li ; Sheng-Jen Wang ; Yen-C

Author_Institution

MediaTek, Hsinchu, Taiwan

fYear

2015

fDate

22-26 Feb. 2015

Firstpage

1

Lastpage

3

Abstract

A 4K×2K H.265/HEVC video codec chip is fabricated in a 28nm CMOS process with a core area of 2.16mm². This LSI chip integrates a dual-standard (H.265 and H.264) video codec and a series of prevalent (VC-1, WMV-7/8/9, VP-6/8, AVS, RM-8/9/10, MPEG-2/4) decoders into a single chip. It contains 3,558K logic gates and 308KB of internal SRAM. Moreover, it simplifies intra/inter-rate-distortion optimization (RDO) processes and reduces external bandwidth via line-store SRAM pool (LSSP) and data-bus translation (DBT) techniques. For smartphone applications, it completes real-time HEVC encoding and decoding with 4096×2160 resolution and 30fps, and consumes 126.73mW (0.5nJ/pixel) of core power dissipation at 0.9V, at 494MHz (encoding) and 350MHz (decoding). 1080HD and 720HD resolutions are reported as well. The chip features are summarized in Fig. 18.6.1.

Keywords

SRAM chips; optimisation; smart phones; video coding; CMOS process; DBT techniques; H.265/HEVC codec LSI; HEVC video codec chip; LSI chip; LSSP; RDO process; data bus translation; dual-standard; external bandwidth; internal SRAM; line store SRAM pool; logic gates; multiformat smartphone applications; rate-distortion optimization; single chip; Bandwidth; Codecs; Decoding; Encoding; Large scale integration; Random access memory; Standards;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid- State Circuits Conference - (ISSCC), 2015 IEEE International

Conference_Location

San Francisco, CA

Print_ISBN

978-1-4799-6223-5

Type

conf

DOI

10.1109/ISSCC.2015.7063063

Filename

7063063