Title :
Design of a time-interleaved band-pass ΣΔ modulator for Class-S power amplifier
Author :
Yang Zhao ; Bill Yang Liu ; Zhiliang Hong
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Abstract :
A new time-interleaved band-pass ΣΔ modulator architecture targeted for Class-S power amplifier is presented. To demonstrate the feasibility a 10th order 60MHz bandwidth modulator based on this architecture is designed in a standard 65nm CMOS process. 54dB of signal noise ratio (SNR) is gotten at a sample rate of 1.92GHz through simulation.
Keywords :
UHF power amplifiers; sigma-delta modulation; 10th-order bandwidth modulator; bandwidth 60 MHz; class-S power amplifier; frequency 1.92 GHz; signal noise ratio; size 65 nm; standard CMOS process; time-interleaved band-pass ΣΔ modulator architecture; Band-pass filters; Computer architecture; Modulation; Power amplifiers; Signal to noise ratio; Standards; Transfer functions;
Conference_Titel :
ASIC (ASICON), 2013 IEEE 10th International Conference on
Conference_Location :
Shenzhen
Print_ISBN :
978-1-4673-6415-7
DOI :
10.1109/ASICON.2013.6811868
