Quantitative analysis for high speed interpolated/averaging ADC

Author

He Tang ; Yong Peng ; Xiang Lu ; Hai Wang ; Wang, Aiping

Author_Institution

Sch. of Microelectron. & Solid-State Electron., UESTC, Chengdu, China

fYear

2013

fDate

28-31 Oct. 2013

Firstpage

1

Lastpage

4

Abstract

Interpolated flash ADC has been widely implemented in high-speed systems. However, practical design is really challenging and greatly experienced and trial-and-error oriented. This paper has quantitatively analyzed the resistive interpolation/averaging techniques and gave mathematical equations on how these two techniques affect the system´s performance, like bandwidth and resolution. It also mathematically presents the system´s offset voltages and variations that are caused by resistors mismatch when multiple interpolating stages are applied. This analysis can be used for trade-off consideration and hence optimum ADC design. The analysis is supported by simulation under SMIC 130nm CMOS technology.

Keywords

CMOS integrated circuits; analogue-digital conversion; interpolation; preamplifiers; resistors; SMIC 130nm CMOS technology; averaging techniques; interpolated flash ADC; multiple interpolating stages; offset voltages; resistive interpolation techniques; resistor mismatch; size 130 nm; Bandwidth; CMOS integrated circuits; Equations; Interpolation; Mathematical model; Resistors; Statistical analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC (ASICON), 2013 IEEE 10th International Conference on

Conference_Location

Shenzhen

ISSN

2162-7541

Print_ISBN

978-1-4673-6415-7

Type

conf

DOI

10.1109/ASICON.2013.6811870

Filename

6811870