Advanced Si and SiGe strained channel NMOS and PMOS transistors with high-k/metal-gate stack

Author

Datta, Suman ; Brask, Justin ; Dewey, Gilbert ; Doczy, Mark ; Doyle, Brian ; Ben Jin ; Kavalieros, Jack ; Metz, Matthew ; Majumdar, Amlan ; Radosavljevic, Marko ; Chau, R.

Author_Institution

Components Res., Intel Corp., Hillsboro, OR, USA

fYear

2004

fDate

13-14 Sept. 2004

Firstpage

194

Lastpage

197

Abstract

Sustaining Moore´s Law of scaling Si CMOS transistors requires not only shrinking the transistor dimensions, but also the introduction of new materials and structures. In the future, advanced high performance CMOS transistors are likely to incorporate highly strained Si and SiGe channels for enhanced carrier transport and high-k/metal-gate stacks for low gate leakage. This work describes the recent advances made in integrating strained Si and SiGe channel transistors with high-k/metal-gate stacks for future high performance, low power logic applications.

Keywords

Ge-Si alloys; MOSFET; dielectric thin films; electron mobility; elemental semiconductors; hole mobility; internal stresses; leakage currents; semiconductor materials; silicon; CMOS transistor scaling; HfO₂-TiN; Si; SiGe; biaxial tensile strain; carrier transport; compressively strained channel; electron mobility; high-k/metal-gate stacks; highly strained channels; hole mobility; low gate leakage; low power logic; strained channel NMOS transistors; strained channel PMOS transistors; transistor dimension shrinking; Gate leakage; Germanium silicon alloys; High K dielectric materials; High-K gate dielectrics; Logic; MOS devices; MOSFETs; Moore´s Law; Silicon germanium; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting

Print_ISBN

0-7803-8618-3

Type

conf

DOI

10.1109/BIPOL.2004.1365778

Filename

1365778