Title :
Efficient Modeling and Floorplanning of Embedded-FPGA Fabric
Author :
Chaudhuri, Sumanta ; Danger, Jean-Luc ; Guilley, Sylvain
Author_Institution :
CNRS -LTCI (UMR 5141), GET / Telecom Paris, Paris, France
Abstract :
In this paper we present an automatic design flow for generating customized embedded FPGA (eFPGA) fabric and a domain specific SOC+eFPGA architecture. This design flow encompasses both the eFPGA user and automatic layout generator perspectives. We discuss generic FPGA modeling based on VPR tool, simulation and high-level models of reconfigurable components, and we present an innovative floor-planing for island style FPGAs using rectilinear macros. Several system integration issues are highlighted. Layout of a real life SOC with an embedded RTR FPGA for cryptographic applications, designed with this flow, is also presented.
Keywords :
circuit layout CAD; field programmable gate arrays; system-on-chip; SOC; VPR tool; cryptographic applications; embedded-FPGA fabric; floorplanning; reconfigurable components; rectilinear macros; Computer architecture; Costs; Delay; Fabrics; Field programmable gate arrays; Logic design; Microprocessors; Programmable logic arrays; Programmable logic devices; Timing;
Conference_Titel :
Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on
Conference_Location :
Amsterdam
Print_ISBN :
978-1-4244-1059-0
Electronic_ISBN :
978-1-4244-1060-6
DOI :
10.1109/FPL.2007.4380741
