Run-Time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II Pro

Reconfigurable computing entails the utilization of a general-purpose processor augmented with a reconfigurable hardware structure (usually an FPGA). Normally, a complete reconfiguration is needed to change the functionality of the FPGA even when the change is minor. Moreover, the complete chip needs to be halted to perform the reconfiguration. Dynamic partial reconfiguration (DPR) provides the possibility to change certain parts of the hardware while other parts of the FPGA remain in use. In this paper, we propose a solution using dynamic partial reconfiguration which provides a methodology to generate bitstreams for removal of ´old´ hardware modules, and placement and routing of new hardware modules within an FPGA. Hardware modules may reside at any location and our solution can connect the additional functionality to the remaining running parts of the chip. In addition, bus macros are no longer necessary and we use the Xilinx tools only for generating the modules. We implemented our solution on a Xilinx Virtex-II Pro series FPGA, specifically the XC2VP30 on the XUP board, and demonstrated that the solution is fully functional.