Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications

Since the 1990s reusable functional blocks, well known as IP-Cores, have been integrated on one silicon die. These systems-on-chip (SoC) used a bus-based system for intermodule communication. Technology, performance and flexibility issues require the introduction of a novel communication system called network-on-chip (NoC). Around 1999 this method was introduced and since then has been investigated by several research groups with the aim to connect different IP-Cores through an effective, flexible and scalable communication network. Exploiting the flexibility of FPGAs, the run-time adaptivity through run-time reconfiguration, opens a new area of research by considering dynamic and partial reconfiguration. Since software parts of an electronic system can also be included into reconfigurable hardware by integration of IP-based microcontrollers, the reconfigurable architecture provides a flexible, multi-adaptive heterogeneous platform for HW / SW Co-designs. This paper presents an approach for exploiting dynamic and partial reconfiguration with Xilinx Virtex-II FPGAs for an adaptive circuit switched network-on-chip and the related techniques for adapting the system during run-time to the requirements of the presented image processing application.