Title :
SoPC Architecture for a Key Point Detector
Author :
Chati, H.D. ; Muhlbauer, F. ; Braun, T. ; Bobda, C. ; Berns, K.
Author_Institution :
Kaiserslautern Univ. of Technol., Kaiserslautern
Abstract :
The design and implementing of a key point detector on embedded reconfigurable hardware is investigated. The major challenges are efficient hardware/software partitioning of the key point detector algorithm, data flow management as well as efficient use of memory, bus and processor. We present a modular and manual hardware/software co-design, with its implementation on a Xilinx XUP-Virtex II Pro board to solve these issues.
Keywords :
data flow analysis; embedded systems; hardware-software codesign; reconfigurable architectures; system-on-chip; SoPC architecture; Xilinx XUP-Virtex II Pro board; data flow management; embedded reconfigurable hardware; hardware-software codesign; hardware-software partitioning; key point detector; key point detector algorithm; systems on programmable chip; Detectors; Digital signal processing chips; Embedded system; Field programmable gate arrays; Hardware; Navigation; Object detection; Partitioning algorithms; Robots; Signal processing algorithms;
Conference_Titel :
Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on
Conference_Location :
Amsterdam
Print_ISBN :
978-1-4244-1060-6
Electronic_ISBN :
978-1-4244-1060-6
DOI :
10.1109/FPL.2007.4380751
