Title :
A fast and accurate automatic frequency calibration scheme for frequency synthesizer
Author :
Yan Dun ; Jiancheng Li ; Songting Li ; Xiaochen Gu ; Chong Huang
Author_Institution :
Sch. of Electron. Sci. & Eng., Nat. Univ. of Defense Technol., Changsha, China
Abstract :
A fully integrated 2.8-3.4 GHz frequency synthesizer that employs a novel automatic frequency calibration (AFC) is presented. The AFC is consists of a frequency error detector (FED) and a finite state machine (FSM). The error between VCO output frequency and the target frequency is calculated quickly and accurately due to the novel topology of PED which employs a utility phase detector (PD). Then a binary search algorithm is used by FSM to adjust capacitor´s code according to the frequency error. Finally the center frequency which is closest to the target frequency is found out as the optimal tuning curve. The total calibration cost only 0.611 μs. The frequency synthesizer is fabricated in 0.18-μm CMOS process and exhibits phase noise of -87.72 dBc/Hz at 10 KHz offset and -95.28 dBc/Hz at 100 kHz offset, while consuming 18 mW from a 1.8 V supply.
Keywords :
CMOS integrated circuits; UHF integrated circuits; calibration; frequency synthesizers; AFC; CMOS process; FED; FSM; PD; PED topology; VCO output frequency; automatic frequency calibration scheme; binary search algorithm; capacitor code; center frequency; finite state machine; frequency 2.8 GHz to 3.4 GHz; frequency error detector; fully integrated GHz frequency synthesizer; optimal tuning curve; power 18 mW; size 0.18 mum; target frequency; utility phase detector; voltage 1.8 V; Calibration; Capacitors; Frequency synthesizers; Phase locked loops; Tuning; Voltage-controlled oscillators; automatic frequency calibration; frequency synthesizer; phase-locked loop;
Conference_Titel :
ASIC (ASICON), 2013 IEEE 10th International Conference on
Conference_Location :
Shenzhen
Print_ISBN :
978-1-4673-6415-7
DOI :
10.1109/ASICON.2013.6811885
