RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator for the Microblaze Processor

A high performance RLS lattice filter with evaluation of an unknown order of identified system was implemented as an accelerator PCORE for Xilinx EDK. The accelerator hardware can fully exploit parallelisms in the algorithm and remove load from a microprocessor. The EDK integration allows effective programing and debugging of a hardware accelerated DSP applications. The optimal logarithmic number system implementation of the RLS lattice IP core was used. Additionally, the extension by the order probability evaluation was implemented. Then, the core was wrapped in the System Generator. Finally, the generated EDK PCORE was modified to independent clock operation. Implemented solution makes possible evaluation of the RLS lattice filter of order 256 at 8 kHz input data rate in the best case. At the same lime the order probability can be maintained. The implementation outperforms software solution up to 74 times and it is also performing 40% faster than other known solutions.