NoC Implementation in FPGA using Torus Topology

With the increasing capacity of FPGAs following the Moore´s law, it is possible to build in a single FPGA, a large system on chip (SoC) composed by several cores. Their performances depend strongly on their interconnection structure. Traditional and hierarchical busses are not suitable to be used. The Networks on Chip (NoC), due to their characteristics such as scalability, flexibility, high bandwidth, have been proposed as a valid approach to meet communication requirements in SoC. Most of the current NoCs uses mesh topology. With mesh topology/, central channels are significantly solicited. This often leads to the congestion of the center area of the mesh. The solution for such situation is to add routers in the mesh or to use torus topology which, with the symmetry introduced on the routers in the opposite edges, has a good behavior to face congestion, and this, with a small increase of resources. In this paper, we propose a scalable implementation of a NoC for FPGA using torus topology. We proposed router architecture, a routing algorithm and a solution to the problem introduced by the long wires in torus topology.