22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS

To meet increasing demands for server computational power, high-density, multilane links with a data rate exceeding 25Gb/s/lane are needed. An optical transceiver with a retiming capability would significantly enhance the usability of the link by extending the reach. Such optical transceivers should operate without an external clock source since a small form factor is imperative. The optical link we develop has a four-lane configuration that consists of an electrical-to-optical (E/O) converter and an optical-to-electrical (O/E) convertor (Fig. 22.7.1). Both the E/O and O/E convertors are equipped with a per-lane reference-less clock-and-data recovery (CDR) circuit that enables independent operation of each lane. The transceiver pitch is 250μm/lane, which matches the fiber pitch of the optical-fiber array used in the link. Since the jitter added by the CDR should be minimized in retimer applications, an LC-VCO is a preferable choice for clock-signal generation. At this transceiver pitch, however, the coupling through mutual inductances between LC tanks has a significant impact on the CDR characteristics. To address this concern, we analyze the impact of inter-VCO coupling and design the CDR so that the coupling does not affect the CDR performance. Each lane of the E/O convertor consists of a continuous-time linear equalizer (CTLE), a CDR, and a VCSEL driver with a two-tap feed-forward equalizer (FFE) (Fig. 22.7.1). Each lane of the O/E convertor has a trans-impedance amplifier (TIA) stage followed by a limiting amplifier (LA), a CDR, and an electrical-line driver with a two-tap FFE. All the CDRs have an identical design consisting of a flip-flop for the data decision, a selector for bypass-mode operation, a Pottbacker type phase-frequency detector (PFD) [1], a charge pump (CP), a lag-lead filter, and a quadrature LC-VCO (QVCO). During the bypass mode, the CDR loop is set into a power-down mode where the VCO does not oscillate.