Study on L2 cache of multi-core processor and optimization for embedded

L2 cache is an important part of the modern microprocessor architecture. The emergence and application of multi-core processors puts forward higher and more complex requirements for cache architecture design. Meanwhile, the multi-core processors begin to appear in embedded fields, which have special requirements. Therefore, designing high-efficiency L2 cache structure becomes one of the key technologies in multi-core processors designs, especially in embedded fields. Based on the multi-core processors OpenSPARC T1, this paper analysed the structures and functions of L2 cache, then studied the implementation of relevant source codes. In order to adapt embedded needs, on the basis of modifying source codes, this paper conducted some simulations to discuss how buffer-size parameters could influence the performance of L2 cache. According to the conclusions and embedded applications, the paper made certain optimization of the buffers in L2 cache for embedded.