• DocumentCode
    2065907
  • Title

    A new splitting graph construction algorithm for SIAR router

  • Author

    Jinming Zhao ; Hailong Yao ; Yici Cai ; Qiang Zhou

  • Author_Institution
    Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
  • fYear
    2013
  • fDate
    28-31 Oct. 2013
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    With the increasing need of the SoC (System on a Chip) design automation tools, analog routing is attracting more and more attention. An interactive analog router called SIAR based on splitting graph model was presented in [15]. Based on SIAR, this paper presents a new splitting graph construction (SGC) algorithm to speed up the graph construction process, and thus speed up the whole analog routing process. The presented SGC algorithm has the following features: (1) auxiliary points are added according to the obstacles´ corner points, (2) there is no need to construct all the grids along the boundaries of the expanded obstacles, (3) a fast polygon-to-rectangle conversion algorithm is adopted to directly construct the splitting tiles needed by the splitting graph. Experimental results are promising and show 2× speedup on average.
  • Keywords
    analogue integrated circuits; graph theory; network routing; system-on-chip; SGC algorithm; SIAR router; SoC design automation tools; analog routing; polygon-to-rectangle conversion algorithm; spillting graph-based interactive analog router; splitting graph construction algorithm; splitting graph model; splitting tiles; system on a chip; Algorithm design and analysis; Computational modeling; Design automation; Routing; Runtime; System-on-chip; Tiles;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC (ASICON), 2013 IEEE 10th International Conference on
  • Conference_Location
    Shenzhen
  • ISSN
    2162-7541
  • Print_ISBN
    978-1-4673-6415-7
  • Type

    conf

  • DOI
    10.1109/ASICON.2013.6811918
  • Filename
    6811918