Title :
25.2 A 2.2GHz −242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture
Author :
Siriburanon, Teerachot ; Kondo, Satoshi ; Kimura, Kento ; Ueno, Tomohiro ; Kawashima, Satoshi ; Kaneko, Tohru ; Wei Deng ; Miyahara, Masaya ; Okada, Kenichi ; Matsuzawa, Akira
Author_Institution :
Tokyo Inst. of Technol., Tokyo, Japan
Abstract :
This paper presents an all-digital phase-locked loop (PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC). It consists of an 18b Class-C digitally-controlled oscillator (DCO), 4b comparator, digital loop filter (DLF), and frequency-locked loop (FLL). Implemented in 65nm CMOS technology, the proposed PLL reaches an in-band phase noise of -112dBc/Hz and an RMS jitter of 380fs at 2.2GHz oscillation frequency. An FOM of -242dB has been achieved with a power consumption of only 4.2 mW.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; digital phase locked loops; integrated circuit noise; phase noise; ADC-PLL; CMOS technology; DLF; FLL; RMS jitter; all-digital phase-locked loop; analog-to-digital converter; class-C DCO; class-C digitally-controlled oscillator; comparator; digital loop filter; digital subsampling architecture; frequency 2.2 GHz; frequency-locked loop; in-band phase noise; oscillation frequency; power 4.2 mW; power consumption; size 65 nm; voltage-domain digitization; word length 18 bit; word length 4 bit; Frequency locked loops; Frequency modulation; Jitter; Phase locked loops; Phase noise; Tuning;
Conference_Titel :
Solid- State Circuits Conference - (ISSCC), 2015 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4799-6223-5
DOI :
10.1109/ISSCC.2015.7063115
