A 65-nm CMOS P-well/Deep N-well avalanche photodetector for integrated 850-nm optical

Author

Quan Pan ; Zhengxiong Hou ; Yipeng Wang ; Yue, C. Patrick

Author_Institution

Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Hong Kong, China

fYear

2013

fDate

28-31 Oct. 2013

Firstpage

1

Lastpage

4

Abstract

A silicon avalanche P-well/Deep N-well photodetectors is fabricated in standard 65-nm CMOS technology without any process modification. By adopting the lightly doped P-well as the P-terminal, a wider depletion region is achieved in a deeper position from the silicon surface. This photodetector achieves a -3-dB bandwidth of 1.1 GHz and a responsivity of 160 mA/W at 12.3 V with 850 nm light input. An integrated receiver using the proposed APD is able to operate at 4 Gbps.

Keywords

CMOS integrated circuits; avalanche photodiodes; elemental semiconductors; integrated optoelectronics; optical fabrication; optical receivers; photodetectors; silicon; APD; CMOS P-well-deep N-well avalanche photodetector; CMOS technology; P-terminal; Si; bit rate 4 Gbit/s; depletion region; frequency 1.1 GHz; integrated optics; integrated receiver; responsivity; size 65 nm; voltage 12.3 V; wavelength 850 nm; CMOS integrated circuits; CMOS technology; Junctions; Optical receivers; Photodetectors; Silicon; Standards; CMOS Photodetector; CMOS integrated optical receiver; avalanche photodetector;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC (ASICON), 2013 IEEE 10th International Conference on

Conference_Location

Shenzhen

ISSN

2162-7541

Print_ISBN

978-1-4673-6415-7

Type

conf

DOI

10.1109/ASICON.2013.6811921

Filename

6811921