DocumentCode
2066279
Title
Development of silicon module with TSVs and global wiring (L/S=0.8/0.8µm)
Author
Sunohara, Masahiro ; Shiraishi, Akinori ; Taguchi, Yuichi ; Murayama, Kei ; Higashi, Mitsutoshi ; Shimizu, Mitsuharu
Author_Institution
Technol. & Applic. Dev. Dept., Shinko Electr. Ind. Co., Ltd., Nagano
fYear
2009
fDate
26-29 May 2009
Firstpage
25
Lastpage
31
Abstract
In recent years, in order to achieve high density and high transmission speed between chips, various kinds of silicon modules have been developed. Our purpose is the development of silicon module in which several chips are mounted on the silicon substrate with Cu-Through Silicon Vias (Cu-TSVs) and fine multilayer Cu wirings such as global layer of devices. Since silicon substrate has a quite flat and smooth surface, fine wirings such as the global layer of devices can be formed. Furthermore, silicon interposer can be applied to a substrate, which show high reliability of micro bump interconnection for the reason of its same Coefficient of Thermal Expansion (CTE) with silicon devices. In this paper, key technologies required for the silicon interposer, that is, fabrication of submicron wiring on the silicon interposer, 1st level interconnection by Transient Liquid Phase (TLP) diffusion bonding, stress reduction at 2nd level interconnection using "Trenched Air Gap (TAG)-TSV" are reported. Finally signal integrity and stability of power/ground delivery for logic devices are also described.
Keywords
copper; diffusion bonding; interconnections; logic devices; microassembling; reliability; silicon; surface mount technology; thermal expansion; wiring; Cu-Si; Cu-through silicon vias; TSVs; coefficient-of-thermal expansion; fine multilayer copper wirings; global wiring; logic devices; microbump interconnection; mounting; power-ground delivery; reliability; signal integrity; silicon interposer; silicon module; silicon substrate; stress reduction; transient liquid phase diffusion bonding; trenched air gap; Dielectrics; Polymers; Production; Silicon; Stability; Stacking; Through-silicon vias; Throughput; Wafer bonding; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference, 2009. ECTC 2009. 59th
Conference_Location
San Diego, CA
ISSN
0569-5503
Print_ISBN
978-1-4244-4475-5
Electronic_ISBN
0569-5503
Type
conf
DOI
10.1109/ECTC.2009.5073992
Filename
5073992
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