• DocumentCode
    2066449
  • Title

    Design and analysis of nano-scale bulk FinFETs

  • Author

    Jong-Ho Lee ; Kyu-Bong Choi ; Jongmin Shin

  • Author_Institution
    Dept. of ECE, Seoul Nat. Univ., Seoul, South Korea
  • fYear
    2013
  • fDate
    28-31 Oct. 2013
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    Design of 14 nm bulk FinFET is discussed and some properties are analyzed physically. The source/drain junction depth is the most important parameter to reduce off-current, and a punchthrough barrier of a peak concentration higher than ~2×1018 cm-3 should be formed just underneath the junction depth at the same time. Uniform body doping concentration needs to be designed to have a doping in the range of 2~4×1017 cm-3. The source/drain contact resistance can be reduced by increasing metal contact area on the source/drain region. The drain current fluctuation with the capture and emission of an electron in a trap inside the gate oxide is less than 2% at a VGS-Vth of 0.1 V, and increases slightly due to the increase of coupling as fin width decreases.
  • Keywords
    MOSFET; contact resistance; nanoelectronics; semiconductor device models; semiconductor doping; drain current fluctuation; metal contact area; nanoscale bulk FinFET; off-current reduction; size 14 nm; source-drain contact resistance; source-drain junction depth; uniform body doping concentration; Contact resistance; Doping; Electron traps; FinFETs; Junctions; Logic gates; Metals;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC (ASICON), 2013 IEEE 10th International Conference on
  • Conference_Location
    Shenzhen
  • ISSN
    2162-7541
  • Print_ISBN
    978-1-4673-6415-7
  • Type

    conf

  • DOI
    10.1109/ASICON.2013.6811940
  • Filename
    6811940