A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals

Leakage power dissipation becomes a dominant component in operation power in nanometer devices. This paper describes a design methodology to implement runtime power gating in a fine-grained manner. We propose an approach to use sleep signals that are not off-chip but are extracted locally within the design. By utilizing enable signals in a gated clock design, we automatically partition the design into domains. We then choose the domains that will achieve the gain in energy savings by considering dynamic energy overhead due to turning on/off power switches. To help this decision we derive analytical formulas that estimate the break-even point. For the domains chosen, we create power gating structure by adding power switches and generating control logic to the switches. We experimentally built a design flow and evaluated with a synthesizable RTL code for a microprocessor and a 90nm CMOS device model both used in industry. Results from applying to a datapath showed that the break-even point that achieves the gain exists in the number of enables controlling the power switch. By applying the domains controlled by up to 3 enables achieved the active leakage savings by 83% at the area penalty by 20%.