Interconnect Considerations For High Performance Network on Chip Designs

Network-on-a-Chip (NoC) is an emerging design style that involves building an on-chip network to link together the logic blocks on a complex system-on-a-chip. The result is any-to-any connectivity for complex data flows and, in early designs, a roughly 3X performance increase over legacy bus-based SoCs. The key design concept in a NoC is replacing the bus with an interconnect switch to link together the autonomous logic blocks. This design is an evolution of the globally asynchronous, locally synchronous (GALS) chip design. This presentation will discuss NoC architecture issues and the use of Fulcrum´s Nexus on-chip interconnect technology as the central switching function in these devices. An elegant solution for this application, Fulcrum´s Nexus is a 2.5Tbps non-blocking crossbar with up to 16 independent full-duplex ports, each capable of 160 Gbps of throughput. Nexus is designed using Fulcrum´s patented circuit technology that gives the switch an extraordinarily low 3 ns latency, a modest power consumption level that is directly related to activity (300Gb/W) and an ultra small 2 mm × 2mm area. A Nexus-based GALS architecture provides the foundation for efficiently partitioning the massive amount of transistors available in next-generation, small geometry NoCs. It is estimated that these devices can support as many as two-dozen IP blocks, as compared to 6 or 8 in a typical 130 nm chip design. This will lead to logic blocks separated by very long wires.